Texas Instruments LFN Series Sample & Hold Amplifiers are available at Mouser Electronics. Mouser offers inventory, pricing, & datasheets for Texas. lf Sample & Hold Amplifiers are available at Mouser Electronics. Mouser offers inventory, pricing, & datasheets for lf Sample & Hold Amplifiers. Understand the working of LF IC (sample-and-hold circuit). • Describe the concept of sampling a time varying signal. • Obtain the sampled and hold otuput.

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This demonstrates that the droop is caused by a constant leakage current, and is not an exponential RC decay.

The next most important characteristic is “dielectric absorption” or hysteresis in the dielectric constant. The transition voltage is 1. The acquisition time is the time for the internal nodes to settle, and the output to be within, say, 0.

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For us, we want to refer the logic to ground by connecting pin 7 to ground, and apply a positive input to pin 8 for the sample state. For most normal uses, a value of 0. For a hold capacitor of 0. This is not a very convenient way to control the JFET, but it works for a demonstration. This gain error is less than 0. This droop is caused mainly by a constant leakage current, and can be predicted fairly well, so that corrections can be made for it if desired.

Apply an input voltage with a potentiometer, and watch the output voltage track it while the gate is connected to the drain. This requires the opposed diodes that “catch” the output of the first op-amp when the feedback loop is broken in the “hold” state.


The capacitor voltage changes as the dielectric “relaxes,” as well as when charge is supplied or taken away.

Measure the time required for it to fall by 1 V. The switch is made from a JFET, which does very well. In the test, I used my debounced pushbutton for the logic signal, choosing the normally-low output. This corresponds to a leakage current of only 33 pA, an excellent result.

The control logic input is applied to a differential amplifier to allow interfacing with various logic families. Even if the times are taken into account, the accuracy of the output depends on several more parameters.

The type of capacitor used is important. There is a settling time after the hold command until the output is within 1 mV of its steady value. Selection of the hold capacitor is an important matter. The larger the hold capacitance, the smaller is the droop. For the LF, this is about 0. In fact, if the input voltage to be digitized is varying, a sample-and-hold circuit is mandatory. Finally, there is droop as the hold capacitor voltage declines steadily in the “hold” state.

The LF is, however, an excellent circuit suitable for most peaceful requirements. In this page, the principle of a sample-and-hold circuit is explained lf38 illustrated, and the practical use of the LF monolithic sample-and-hold circuit is described. The smaller the hold capacitor, the more quickly it can be charged and the smaller the acquisition time.

To sample, the gate is connected to the drain or the sourceand to hold, the gate is connected to -V. The similarity to our test circuit is obvious. The LF is connected as shown at the left. For the LF, with a 0. Bipolar op-amps are not suitable, because the input base currents are too large.

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Times from the hold command are measured from the 1. The ld398 of the LF allow it to be up to pA.

There is, therefore, a tradeoff in selection of hold capacitor lf3398. Polypropylene has the least hysteresis of all, and is the best choice for a hold capacitor, but any of the three will give adequate results. It is obvious that the capacitor should have small leakage, so all electrolytics, whether aluminum or tantalum, are excluded. The voltage kept on decreasing, until it reached some internal saturation value at Buffer a slow signal with an LS I found about 5 minutes, so the droop rate is 3.

When the gate is lt398 to -V, the output will freeze, and you will note that it droops slowly but steadily. These diodes then require the 30k resistor to avoid overloading the output amplifier. Lf3988 or HC logic will do very well.

I found that it took 28 minutes to decline to 0. The leakage current is found to be 30 pA. Note that we did not do much worse than this with our discrete circuit.

If you plot the output voltage versus time, you will find a straight line with a slope of What happens is this: Secondly, there is a finite jump in the output voltage called the hold step when the hold command is issued.

The acquisition time depends on the size of the hold capacitor. If you need better specs, there are the more expensive LF and LF which mainly give an extended temperature rangeand the LFA, with tightened specs.